Recently, technologies for manufacturing MOS (Metal Oxide Semiconductor) devices have rapidly developed, so that small-sized, high-performance MOS devices can be obtained. In order to achieve such small-sized, high-performance MOS devices, the technologies relating to the thickness of the gate oxide layer, the source/drain regions, and the channel region must be improved.
Because MOS transistors are highly integrated, a short channel effect (SCE) occurs. In order to suppress the short channel effect, the thickness of the gate oxide layer must be small. In addition, the source/drain regions must be formed with shallow junctions to reduce a charge sharing effect. In addition, in order to suppress the short channel effect of the MOS transistor, a retrograde ion implanting process or a halo ion implanting process may be performed to change the doping profile of the channel.
A prior art method of manufacturing a conventional MOS transistor will now be described with reference to FIGS. 1A to 1D. Referring to FIG. 1A, an active region where a MOS transistor is to be formed is defined by forming isolation layers 110 in an n-type semiconductor substrate 100. (Alternatively, instead of the n-type semiconductor substrate 100, a p-type semiconductor substrate may be used. In such an approach, an n-type well region is formed in the p-type semiconductor substrate). Next, a gate insulating layer 120 and a gate 130 are sequentially formed on the active region of the substrate 100. The active region under the gate 130 serves as a channel region.
Referring to FIG. 1B, a first ion implanting process is performed to form lightly doped drain (LDD) regions 141a, 141b within the substrate 100 on opposite sides of the gate 130. The first implanting process is performed by implanting p-type impurity ions of low concentration 141 (e.g., boron (B) or BF2 ions) in the vertical direction with respect to the substrate 100. Although not shown in the figure, an ion implanting buffer layer may be formed on a surface of the substrate 100 prior to performing the first ion implanting process.
Referring to FIG. 1C, in order to reduce the short channel effect, a second ion implanting process is performed to form halo regions 142a, 142b in contact with the LDD regions 141a, 141b within the substrate 100. The halo regions 142a, 142b are formed inwardly of the LDD regions 141a, 141b by implanting n-type impurity ions 142 (e.g., arsenic (As) ions) in a tilted direction with respect to the substrate 100.
Referring to FIG. 1D, spacers 150 are formed on opposite side walls of the gate 130. In the illustrated process, the spacers 150 comprise a nitride layer or a double-stacked layer comprising an oxide layer and a nitride layer. Next, a third ion implanting process is performed to form source/drain regions 143a, 143b within the substrate 100 on opposite sides of the spacers 150. The third ion implanting process is performed by implanting p-type impurity ions at a high concentration 143 (e.g., B ions) in a vertical direction with respect to the substrate 100. As shown in FIG. 1D, the source/drain regions 143a, 143b are formed to a deeper level than the LDD regions 141a, 141b. The p-type impurity ions 143 are also implanted into the gate 130 to dope the gate 130.
In the conventional method of manufacturing the MOS transistor described above, in order to suppress the occurrence of the short channel effect due to the high integration density, the source/drain regions 143a, 143b must be formed with the shallow junction. For this reason, a low ion implanting energy is used during the third ion implanting process.
However, if the ion implanting energy is low, the gate 130 is not sufficiently doped and, thus, depletion of the gate increases. In addition, the p-type impurity ions 143 implanted into the gate 130 may penetrate into the channel region during the subsequent thermal treatment process. This penetration may deteriorate electrical properties such as threshold voltages and channel currents of the MOS transistor.